(Invited) Generation-Recombination Noise in Advanced CMOS Devices

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It is well-known that the noise power spectral density of scaled devices increases for smaller area. At the same time, the character of the noise spectrum changes from predominantly 1/f-like to Lorentzian, characterized by a plateau at low frequencies (f<fc) and a roll-off following 1/f2 [1]. Such a noise is related to trap-assisted generation-recombination events, with characteristic or corner frequency fc, which is related to the emission (te) and capture (tc) trap time constant of the carriers from and to the defect centre. In scaled CMOS transistors, two different behaviours of fc with respect to the gate voltage (VGS) can be distinguished: as shown in Fig.1 some traps exhibit little VGS dependence, while others show a more or less exponential increase with VGS [2]-[4]. In the first case, it is believed that the traps are in the depletion region of the semiconductor, while the second case corresponds to traps in the gate dielectric [1],[2] and is also known as Random Telegraph Noise (RTN). In this paper, it is shown how the Lorentzian parameters can be used to extract more information on the underlying traps. In the case of an oxide trap, it will be shown that the exponential slope at low or at high VGS corresponds with ae or ac, i.e., the exponential slope of the emission and capture time constant. This is illustrated by Figs 2 and 3. From these exponential coefficients, the trap depth in the oxide can be derived, as an alternative for the time constant ratio tc/te. In principle, one can rely then on the variation of fc with temperature T to extract the activation energy for carrier capture (high VGS) and/or emission (low VGS). In the case of semiconductor traps, the shift of fc with T, illustrated in Fig. 4 for a Si bulk nFinFET can be employed for the construction of an Arrhenius plot, like in Fig. 5. The slope yields the activation energy while a capture cross section can be derived from the intercept with the y-axis. This can also be applied to relaxed (r-) or strained (s) Ge pMOSFETs fabricated in different substrate types [6]. As shown in Fig. 6, the nature of the substrate has a strong impact on the corresponding surface trap density.