(Invited) Expansion Behavior of Single BPD Loop Causing Stacking Fault Multiplication in 180 Μm Thick 4H-SiC Epitaxial Layers

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Silicon carbide (4H-SiC) devices with blocking voltage rating up to 3.3 kV have been successfully commercialized [1]. This is due to availability of low cost and low defectivity epitaxial layers with a thickness of up to 30 µm that are need for devices up to 3.3 kV. However, for grid scale and defense applications, higher voltage (10-30 kV) SiC devices such as insulated gate bipolar transistors (IGBTs) are needed. For this, thicker epitaxial layers, ranging from 100 – 250 µm thick, are required withstanding the higher blocking voltage. Such epitaxial layers are prone to formation of basal plane dislocation loops due to a combination of higher thermal stress and lattice mismatch between the lightly doped epitaxial layers and highly doped substrates [2-4]. These BPD loops can expand and form stacking faults (SFs) during device operation, which leads to forward voltage degradation in bipolar devices such as IGBTs as well as higher reverse bias leakage in both unipolar and bipolar devices. This effect will be more severe with the presence of multiple SFs in the device area. In this work, we perform an investigation of a single BPD loop that interacts with several threading mixed dislocations (TMDs) upon carrier injection and creates at least 15 stacking faults.For this work, we used 180 µm thick SiC epitaxial layers with n-doping of 5x1014 cm-3. This was commercially grown on 150 µm 4H-SiC substrates with an ~1µm thick highly n-doped buffer layer. A single BPD loop was identified in the wafer using ultraviolet photoluminescence (UVPL) imaging. High resolution X-ray topography (XRT) of the BPD loop was performed to investigate its formation using Rigaku XRTMicron system with Mo radiation in depth-resolved section geometry with g=11-20 and g=1-100 Bragg conditions. The BPD loop was expanded with carrier injection using 355nm UV excitation, and concurrently imaged with UVPL imaging. A series of successive images were collected for a duration of ~30 mins. This was followed by XRT imaging of the BPD loop after the expansion.From the initial UVPL images, the single BPD loop was observed to have faulted into a single SF, and after the ~30 min exposure, at least 15 SFs were observed from the same region. During the SF expansion, the Si-core partial dislocations bounding the SF interact with several TMDs, including mostly straight as well as tilted TMDs. These interactions form both locked partial dislocation dipoles (PDDs) as well as mobile PDDs, which freely glide as new SFs. It was also observed that an initial BPD partial interacts successively with two tilted TMDs and leaves behind a mixed partial dislocation, which later faults into a new SF. Several other interactions between the expanding BPD partials and TMDs will be presented. From the section XRT images, the BPD loop was found to originate from a single BPD in the substrate with a single interfacial dislocation (ID), and the BPD appeared to loop back towards the substrate/epilayer interface. The other end of the BPD loop did not have an ID. Detailed investigation of the formation and expansion behavior of the BPD loop will be presented.