Abstract

The IEEE International Roadmap for Devices and Systems (IRDS) for More Moore devices summarises the Logic Device state of play very effectively; the FinFET is the key device architecture that could enable logic device scaling until 2025. Increasing fin height while reducing number of fins at unit footprint area is an effective solution to improve performance. It is forecasted that the parasitics will remain as a dominant term in the performance of critical paths. For reduced supply voltage, a transition to gate-all-around (GAA) structures such as lateral nanowires or nanosheets will be necessary to improve electrostatics. Lateral GAA structure would eventually evolve in to the vertical GAA structure to gain back the performance loss due to increasing parasitics at tighter pitches. In this paper we will consider doping techniques based on ion implant, solid-source in-diffusion, liquid-source in-diffusion, and gas-source in-diffusion for these device technologies.

Talk to us

Join us for a 30 min session where you can share your feedback and ask us any queries you have

Schedule a call

Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.