(Invited) Doping Considerations for Finfet, Gate-All-Around, and Nanosheet Based Devices

Abstract

The IEEE International Roadmap for Devices and Systems (IRDS) for More Moore devices summarises the Logic Device state of play very effectively; the FinFET is the key device architecture that could enable logic device scaling until 2025. Increasing fin height while reducing number of fins at unit footprint area is an effective solution to improve performance. It is forecasted that the parasitics will remain as a dominant term in the performance of critical paths. For reduced supply voltage, a transition to gate-all-around (GAA) structures such as lateral nanowires or nanosheets will be necessary to improve electrostatics. Lateral GAA structure would eventually evolve in to the vertical GAA structure to gain back the performance loss due to increasing parasitics at tighter pitches. In this review we will consider doping techniques based on ion implant, solid-source in-diffusion, liquid-source in-diffusion, and gas-source in-diffusion for these device technologies.The problem of doping source-drain regions in Si MOS devices usually boils down to the problem of (1) getting the dopant into the target structure or wafer, (2) activating the dopant by a thermal treatment, (3) controlling the crystal damage and diffusion. In these advanced device architectures, in essence, the surface is a trapping site for dopants. This isn’t too much of a problem if ions are implanted past the surface by beam-line or by plasma-assisted doping processes, however with the in-diffusion based techniques this is a severe issue.