(Invited, Digital Presentation) Heterogeneous Integration of Ultrahigh-Κ Single-Crystalline SrTiO3 Membranes for Two-Dimensional Electronics

Abstract

Even though competitive 2D field-effect transistors (FETs) with the scaled channel dimensions have been demonstrated, it still is a challenge to integrate 2D semiconductors and high-κ dielectrics without deteriorating their interfaces, while decreasing capacitance equivalent thickness (CET) of dielectrics to maintain the gate controllability. In particular, the dielectric/channel interface is one of the predominant factors to affect device performance, including carrier mobility, switching behavior, and drifts of device parameters. This is often caused by the nature of dielectrics used, and the integrating methodologies applied.Typically, high-κ dielectrics used in silicon technology (i.e., Al2O3 and HfO2) are inherited by 2D FETs. The amorphous nature of these oxides makes the elimination of charge scattering and trapping sites at the dielectric/channel interfaces extremely difficult, not to mention that the direct deposition of dielectrics usually damages the 2D channel and results in poor uniformity in sheer thickness. Some interfacial passivation layers and processes have been developed, but they lead to thickening overall CET instead. Alternative approaches with the crystalline dielectric materials such as multilayer hBN and epitaxial calcium fluoride (CaF2), whose surfaces are well-constructed and atomic-flat, have demonstrated the competitive advantages of crystalline dielectric over the conventional amorphous oxides in spite of relatively lower κ values.Here, we demonstrate ultra-scaled 2D FETs with desirable sub-1 nm CET through heterogeneous integration of monolayer CVD MoS2 and quasi-2D single-crystalline SrTiO3 membranes, where the optimized SrTiO3 gate dielectrics exhibit a low gate leakage (J leak < 10-2 A/cm2 at 2.5 MV/cm). Typical transistors manifest good reliability and competitive performance characteristics, including steep subthreshold swings (SS) down to ~70 mV dec-1 and ON/OFF current ratios up to 107, matching low-power specifications suggested by the latest International Roadmap for Devices and Systems (IRDS). In addition, the van der Waals (vdW) interface between quasi-2D dielectrics and 2D semiconductors moderates the unfavorable fringing-induced barrier lowering (FIBL) effect occurring in ultra-scaled Si transistors with very high-κ dielectrics, which broadens the dielectric selection in 2D electronics for future technology node.