Abstract
The relentless downscaling of the semiconductor device feature sizes has resulted in tremendous technological advances such as mobile/portable electronics, internet of things (IOT) just to name a few. New device engineering and dielectric materials with engineered properties are becoming essential in overcoming the issues seen in scaled CMOS devices such as short channel effects (SCE). Mobile device, automotive, IOT, big data, and machine learning will be the growth drivers of the semiconductor industry for the next decades to come. These applications will not be successful without new materials, novel processing and integration schemes. There have been several innovations recently in reducing power such as FinFETs, nanosheets, and nanowires. However, the power supply voltage has not significantly scaled below ~1V due to the physical limitation in transistor operation known as Boltzmann limitation which dictates the inability of scaling down the voltage require to increase the transistor drive current by a decade also known as the subthreshold swing (SS) below 60mV/decade. One solution investigated by device makers and foundries is ferroelectric FET (FeFET). The ferroelectric material acts as a transformer boosting the input voltage hence overcoming the Boltzmann limitation or SS below 60mV/decade. Several scaling boosters are being studied to enable further device performance improvement such as self-aligned gate contact, fully self-aligned via, negative capacitance. In this presentation, applications and challenges associated with implementing high-k dielectrics will be discussed.
Published Version
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