(Invited) Boosting the On-Current of Si-Based Tunnel Field-Effect Transistors

Abstract

Tunnel-FETs (TFETs) have the potential for a sub-60 mV/dec subthreshold swing and therefore allow for scaling the supply voltage beyond the 1 V plateau of metal-oxide-semiconductor FETs (MOSFETs). The latter scaling is a necessary condition for a reduction of the power consumption per transistor. Silicon-based TFETs are the most attractive because they allow for a full re-use of the existing expertise in fabricating silicon MOSFETs. However, the large bandgap of silicon results in low on-currents. Therefore, the incorporation of heterostructures is proposed. In particular, a germanium-source silicon-channel n-TFET and, as complementary p-TFET, an indium(gallium)arsenide-source silicon-channel TFET reach on-currents comparable to MOSFETs. To beat the MOSFET performance and allow ultra-low voltage operation, additional performance boosters are required. We analyze the impact of the device configuration and of heterostructure strain. The former is illustrated with experimental data of all-silicon FinFET-based TFETs.