Abstract
The rapid growth of technologies such as artificial intelligence and autonomous vehicles is fueling a need for more powerful electronic chips, which the semiconductor industry is working to meet with ever-more complex nanoscale device structures. With this growing need for nanostructure fabrication, selective deposition is gaining much attention as an important process to achieve pattern features at the ~10 nm length scale. Both two-dimensional planar geometries and three-dimensional structures will benefit from selective deposition processes, with bottom-up growth strategies providing advantages in reduced process complexity and improved pattern fidelity. In this presentation, we will describe how control over surface chemistry using molecular monolayers can achieve area selective atomic layer deposition (ALD). ALD is a good choice for selective deposition because its chemical specificity provides a means to achieve selectivity on a spatially patterned substrate. In particular, inhibitory layers such as self-assembled monolayers (SAMs) can alter the native surface reactivity, allowing ALD selectivity to be achieved. We will show that this process provides good selectivity for thin deposited films, and demonstrate selective deposition on different materials, including dielectrics and metals such as Cu, Co, W and Ru. Because area selective ALD processes often break down after more than a few nanometers of material is deposited, strategies to overcome the undesired ALD nucleation on the inhibitory layer and achieve significantly higher selectivity in area selective ALD are also important. Two such strategies that improve the final selectivity will be described, including SAM repair between ALD cycles and a self-correcting process in which selective deposition is combined with selective etching. With both approaches, selective ALD of more than 60 nm of metal oxide dielectric material can be achieved. Directions toward new area selective deposition processes will also be described.
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