Abstract
A three dimensional (3D) process for a quantum beam imager is proposed. In this process, chip-on-chip stacking scheme with base chips fabricated by fully depleted silicon on insulator (FD-SOI) technology is concerned. Features of the 3D process are the lower and upper chip electrode connection by Au micro-bump and submicron through buried oxide via (TBV) to connect upper bonding pads which is fabricated in wafer processing of the FD-SOI, instead of generally used through silicon via (TSV). The first trial run of the 3D process using pixel level bump bonding in the quantum beam imager was completed. The laser light response of timing memory in the pixel is confirmed. The results indicate potential of the proposed 3D process for the future quantum beam imager.
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