Investigative analysis of match-line sensing schemes in TCAM for high-speed performance

Abstract

This paper delineates an investigation of TCAM-design techniques for both circuit level and architectural level. In the case of circuit level, low power Match Line sensing techniques and Search Line driving propositions are exhibited. At the architectural level, four processes for curtailing power absorption are introduced. In this paper, 16×16 bit TCAM is designed in 0.18μm CMOS. The hypothesized Match Line sensing scheme truncates power absorption by pruning search time and dampering voltage swing of traditional ones. With respect to the conventional CR-MLSA, the proposed MLSAs delineate the depletion of 56% and 48% for measuring energy. For simulation, 1.8V supply voltage is used.