Abstract
Back-contacted cells offer multiple advantages in regard of reducing module assembling costs and avoiding grid shadowing losses. The investigated emitter-wrap-through (EWT) design is equipped with a front and a rear emitter (Gee et al., Proceedings of the 23th IEEE PVSC, 1993, p. 265). Both emitter areas are electrically connected by small holes drilled into the crystalline silicon wafer. Renouncing on expensive photolithographic steps several techniques appropriate for a low-cost process have been investigated. An increase in J sc of 15% was measured when compared to a conventionally processed reference cell. However, the open-circuit voltage V oc and the fill factor did not improve. Possible reasons for these losses are presented in this paper. The efficiency of one of the best low-cost EWT cells within this work reached 13.6% on Cz-silicon, which is the highest efficiency reported so far for this cell type (Schönecker et al., Proceedings of the Second WCPSEC, 1998, p. 1677).
Published Version
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