Investigation on the Effect of Gate Dielectric and Other Device Parameters on Digital Performance of Silicene Nanoribbon Tunnel FET

Abstract

In this article, silicene nanoribbon (SiNR)based tunneling field effect transistor (TFET) is investigated for low power digital applications. A comprehensive study on the role of gate dielectric and device parameters, such as drain doping, channel length of SiNR TFETs, are carried out to see the performance of digital applications. To achieve higher ION/IOFF ratio and lower subthreshold swing (SS), a detailed investigation is carried out on the equivalent oxide thickness (EOT), channel length, and doping of drain. A digital performance metric comparison of SiNR TFETs with germanium-silicon (Ge-Si), monolayer graphene nanoribbon (MLGNR), and bilayer graphene nanoribbon (BLGNR) TFETs has been performed. It is concluded that SiNR TFETs made of Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> gate dielectric with 0.86 nm effective oxide thickness, 0.5 mM (8 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">12</sup> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-2</sup> ) drain doping concentration, and 5 mM (8 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">13</sup> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-2</sup> ) source doping concentration exhibits lower intrinsic delay, higher ION, higher ION/IOFF ratio, and lower SS at 25 nm channel length.