Investigation on High-Performance CMOS With p-Ge and n-InGaAs MOSFETs for Logic Applications

Suchismita Tewari,Abhijit Biswas,Abhijit Mallik

doi:10.1109/tnano.2015.2390295

Suchismita Tewari, Abhijit Biswas + Show 1 more

https://doi.org/10.1109/tnano.2015.2390295

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CMOS circuits built using Ge-channel p-MOSFETs and InGaAs-channel n-MOSFETs have shown promise for high-performance logic applications. In this paper, we investigate for the first time the performance of such circuits using extensive device simulations. The digital performance of a CMOS inverter is evaluated in terms of noise margins, rise time, fall time, and propagation delay. Furthermore, frequency of oscillations of a three-stage ring oscillator is obtained for varying ratio of the channel width of the p- and the n-MOSFETs, respectively (W p /W n ). Our investigations reveal that the CMOS circuits comprising of p-Ge and n-InGaAs MOSFETs outperform their equally sized Si counterpart. Moreover, superior performance of Ge/InGaAs-based CMOS is obtained for In 0.75 Ga 0.25 As channel with width ratio (W p /W n ) of 10: 1. Also, Ge/InGaAs CMOS is found to lose its advantages over Si CMOS for 5 × 10 12 eV -1 · cm -2 .

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