Abstract
This paper analyzes both experimentally and by simulation the impact of traps on the transfer characteristics of tunnel-FETs (TFETs). The interface trap density in vertical heterojunction TFETs is varied by annealing in hydrogen or deuterium ambient. We show that a high-interface trap density (~2×10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">12</sup> /cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ) results in a peak current in the device transfer characteristic at low-gate bias due to surface generation of carriers. The passivation of interface traps to state-of-the-art densities near 1-2×10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">11</sup> /cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> reduces this peak, but improves only marginally the overall subthreshold swing, indicating that the trap-assisted tunneling responsible for the swing degradation is mainly occurring through bulk traps in these devices.
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