Investigation of the solder void defect in IC semiconductor packaging by 3D computed tomography analysis

Abstract

Flip chip packaging has gained more acceptance; becoming well known in semiconductor packaging industries, mainly due to the increasing demand in the market for small size packages. The application of copper pillar joint in flip chip packaging has contributed to more challenge in complex failure analysis. Solder void defect in between the copper pillar joint area poses a great risk to device malfunction, especially if the device has been used by customer for quite some time. To assess the quality of copper pillar joint, backend semiconductor chip manufacturers normally will apply electrical testing on the production floor for filtering purpose. However, the electrical testing method may still not be sensitive enough to filter out risky samples with minor or less than 50 percent solder joint crack or solder void samples. The conventional failure analysis method commonly applied by backend assembly house is highly dependent on mechanical cross-section to reveal the copper pillar solder joint interfaces, therefore this method still has high risks of defective unit escaping from failure detection. Cross section analysis also has limitation of only capable of providing one plane interface information, which increases the difficulty in finding roots causes. This paper introduces three dimension computer tomography inspections method to overcome the aforementioned limitation and difficulty. The finding in this study shows that this new method can detect solder defects more accurately by calculating the solder void volume and void propagation direction, which can never be achieved by conventional analysis.