Failure analysis challenges and solution for thin package

Abstract

Packaging failure analysis (FA) is becoming more challenging as packaging technology transitions from standard cores to coreless substrates. Substrate thickness has been driven from standard cores at 800 um to thin cores at 380 um on its way to coreless. As a result, substrate mechanical strength has also decreased; therefore, solder joint cracking is a common issue on thin packages due to high package warpage during assembly manufacturing processes that produce strains exceeding the solder joint limit capability. Substrate and the overall thermal coefficient of expansion (CTE) of thin-core or coreless is another major challenge in assembly; its effect on the flip-chip solder joint integrity needs thorough study. Current FA methodology using manual cross-sectioning/polishing provides very limited information. Through novel research on an available concept, AMD Device Analysis was lab able to improve FA methodology by applying a well-known, non-destructive test (NDT) called dye penetrant testing (DPT). The steel and oil-and-gas industries use this methodology widely, and the problem statement is the same in semiconductor packaging: metal integrity inspection. Our modified methodology has been applied semiconductor FA. This paper details the application of DPT in flip-chip package for solder joint crack analysis. DPT builds on the principle of visual inspection, overcoming the limitation of conventional method by enabling complete die solder joint crack analysis. DPT is the first conventional board-level analysis to be introduced to flip-chip packaging.