Investigation of the Gate Bias Stress Instability in ZnO Thin Film Transistors by Low-Frequency Noise Analysis

Abstract

To investigate the electrical instability mechanism under the application of gate bias stress and relaxation, the 1/f noise spectra of two different ZnO thin-film transistors (TFTs) were analyzed. In terms of gate bias dependence (SIDS/IDS), both devices followed a mobility fluctuation model based on the traps in their channel layers prior to and after stress. Device A (channel thickness: 20 nm), recovered its initial noise parameter (αapp) after relaxation, in exact agreement with the current–voltage (I–V) measurement results; this shows that in device A, the dominant phenomenon under the application of stress was temporary charge trapping at grain boundary traps. However, in device B (channel thickness: 80 nm), αapp did not recover its initial values after relaxation, and transfer parameters, such as VTH, mobility, SS, and Nt, degraded after the gate bias stress. Moreover, after the stress, device B showed a reduced gate insulator breakdown voltage. The electrical degradation seen in device B can be explained by trap creation and/or charge injection near channel/gate oxide interfaces, including those within the channel layer.