Investigation of solder creep behavior on wafer level CSP under thermal cycling loading

Abstract

The industry keeps driving further miniaturization of electronic packaging for portable and handheld products, and wafer level chip scaling package (WLCSP) has high potential to fulfill these requirements. Larger chip can accommodate more functions. However, fatigue failure of WLCSP solder joint caused by material coefficient of thermal expansion (CTE) mismatch is getting worse due to chip size increase. Researches of WLCSP design optimization for solder joint reliability enhancement are available in the literature, such as the effect of die thickness and printed circuit board (PCB) thickness, but not detail to the study on solder joint creep behavior along thermal cycling ramp and dwell period. In this paper, the solder joint creep behavior on WLCSP with different die thickness under thermal cycling loading will be studied. This study will leverage an ultra large die, 14mm × 14mm full array WLCSP with 0.4mm ball pitch, 0.25mm ball size and SAC ball material, as test vehicle and apply JEDEC compliant thermal cycling profile with 10 minutes of dwell time and 10 minutes of ramp time for simulation result validation. Finite element models (FEM) with Garofalo-Arrhenius creep constitutive equation is conducted for solder joint creep behavior analysis. The result of the thermal cycling experimental test show good agreement with the FEM model. The FEM result using thin die approach will explain the mechanism of solder joint creep accumulation during thermal cycling loading, and the finding of die to PCB thickness ratio can be design reference for system designer.