Board level WLCSP 3D thermal stress analysis by submodeling of FEA

Abstract

Wafer level Chip Scale Package (WLCSP) fulfills the demand for small, light, and portable handheld electronic devices, and it is one of the most advanced packaging concepts. When the WLCSP was assembled on board level, the connection, i.e. solder joints are generally the critical and challenging issue for the whole device's reliability. In addition to the shape and material of solder joints, the material and structures around the solder joints, such as underfill material, under bumper metal (UBM) and passivation layers can affect the connection's stress field under thermal loadings. In this investigation, the on board level WLCSP with Sn-Ag-Cu solder bump joints was built in 3D model and was analyzed by finite element method. The global model was simulated under one thermal cycling loading according to JEDEC standard. Owing to the ultra-thin thickness of UBM and passivation layers, the submodeling method was used in the finite element analysis to show the detail of stress distribution in the small structures near solder joints. When the structure sizes and material properties of solder joints, underfill and UBM were varied, the parametric analysis showed the trend of the stresses changing in the WLCSP. On the basis of analysis, the possible failure sites and optimization suggestions were obtained.