Investigation of Si nanocluster formation in sputter-deposited silicon sub-oxides for nanocluster memory structures

Abstract

In silicon nanocluster (Si-NC) memories, Si-NC embedded in the gate oxide of an MOSFET are used to store and release electrons thereby modifying the threshold of the transistor. This paper describes the formation of its core functional structure, the Si-NC MOS memory capacitor, by annealing a SiO 2/SiO x ( x<2) stack, deposited onto a thin direct tunneling oxide on silicon by a sputtering method. To achieve a high density of isolated Si-NC, both, the initial silicon excess in the SiO x layer and the thermal annealing treatment must be optimized. Optimum conditions are expected just at the end of the nucleation stage of the NC ensemble. Therefore, the effect of various rapid thermal anneals (RTA) on SiO x /Si structures with different silicon excess x was investigated focusing on two optical methods: infrared absorption and photoluminescence (PL). The rate of nucleation and phase separation were found to depend strongly on both, silicon excess and annealing temperature. The characteristic size dependence of Si-NC PL was used to differentiate annealing regimes yielding NC ensembles being ‘frozen’ in the process of nucleation or in their growth/ripening phase, respectively. Additionally, Si-NC MOS memory capacitors were prepared and characterized using both, optical and electrical tests. The devices prepared under optimized conditions yield a high flat-band shift and good charge retention characteristics.