Abstract
With the aggressively scaled technology, the single-event transient (SET) in the integrated circuits is regarded as one of the critical threats to the system reliability, where the hardening efficiency strongly depends on the randomness of striking positions and process-voltage-temperature (PVT) variations. To enhance the SET robustness and improve the immunity to PVT variations, different layout-based hardening techniques are proposed and compared. Moreover, the tolerance of PVT for hardened layouts and the underlying physics reasons are investigated by technology-computer-aided-design simulations. The simulation reveals that the techniques combining the split active area, gapless well and source, and the selectively implanted deep N-well enable to reduce the transient pulse width as well as mitigate the variations from PVT and hit position.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
