Investigation of PVT variation on single-event transient effect assisted with hardened layout techniques

Abstract

With the aggressively scaled technology, the single-event transient (SET) in the integrated circuits is regarded as one of the critical threats to the system reliability, where the hardening efficiency strongly depends on the randomness of striking positions and process-voltage-temperature (PVT) variations. To enhance the SET robustness and improve the immunity to PVT variations, different layout-based hardening techniques are proposed and compared. Moreover, the tolerance of PVT for hardened layouts and the underlying physics reasons are investigated by technology-computer-aided-design simulations. The simulation reveals that the techniques combining the split active area, gapless well and source, and the selectively implanted deep N-well enable to reduce the transient pulse width as well as mitigate the variations from PVT and hit position.