Investigation of N+ pocket-doped junctionless vertical TFET and its digital inverter application in the presence of true noises

Abstract

This paper reports the investigation of conventional junctionless tunnel FET (JL-TFET) and N+ pocket-doped junctionless vertical tunnel FET (JL-VTFET). The investigation is done by analyzing the effect on the ID–VGS characteristics (a) under a wide range of temperature and (b) in the presence of acceptor interface trap charges. This work also examines the performance of noise and its impact on the digital inverter. Comparison has been made on the TCAD simulated results of both the devices. It is observed that the degradation of drain current (ID) is less in JL-VTFET and also it has better noise performance than that of conventional JL-TFET. Its net drain current noise spectral density (Sid) reaches 10–15 A2/Hz till 1 MHz and decreases with further increase in frequency. The contributions of generation–recombination noise and flicker noise are found to be more in low and moderate frequency, whereas diffusion noise dominates at high frequency. Furthermore, the impact of interface traps is studied using complementary JL-VTFET digital inverter application and compared with the one without interface traps. The transient characteristics show an average delay of 15 ps and 27 ps in the absence and presence of interface traps, respectively.