Abstract
After a long period of research and development high mobility Ge-based materials are being introduced as channel materials of pMOS transistors targeting 5nm node and below [1, 2]. Due to an aggressive scaling, transistors source/drain (S/D) areas are reduced dramatically along with the channel, which has a strong impact on epitaxial layers quality, strain introduction in the channel, contact resistivity, parasitic capacitances, etc. Although standard S/D materials such as SiGe:B and Si:P are being intensively used by the semiconductor industry, other options are being investigated in order to improve the contact resistivity. In the case of Ge based n-MOS transistors SiGe:P attracts attention since it allows a defect free growth on the Ge starting surface, the introduction of tensile stress in the Ge channel and comparably low Rc if sufficiently doped.In this contribution we focus on SiGe:P growth at a very low temperature of 400oC in view of Ge-based devices processing and further 3D device integration which require a considerable reduction of thermal budget. We show that maximum achievable active P concentration (~1e20cm-3) of as grown layers strongly depends on the Ge concentration with the optimal Ge concentration below 45%. For higher Ge concentrations achievable active P concentration is lower. However, it can be significantly improved by means of post epi laser annealing which eventually allows to vary Ge concentration in a broad range of 30 – 70%. Finally, we will demonstrate a selective epitaxial growth, obtained by applying a cyclic deposition and etch routine using Cl2 as an etchant gas (Fig.1).[1] E. Capogreco et al ., Symposium on VLSI Technology, 2019, pp. 94[2] G. Yeap, et al., IEDM 2019, pp. 879Fig.1. Maximal P active concentration as a function of Ge concentration in SiGe grown at 400oC (left), SiGe:P selectively grown in the Source/Drain areas of a Ge finFET device (right). Figure 1
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