Low Temperature Selective Epitaxy of Group-IV Semiconductors for Nanoelectronics

Abstract

Continuous improvement of device performance is becoming very challenging as the transistor dimension approaches the physical limits of scalability. In particular, the source/drain (S/D) layer resistivity and contact resistance at the S/D region became major components for further parasitic resistance reduction [1]. Therefore, layers with high active doping concertation is required for future technology nodes. From another side, novel architectures such as 3D-stacked devices constraints the allowed thermal budget for epitaxy processes [2]. In this work, we will review our recent achievements on LT epitaxy for both Si:P and SiGe:B layers to enable (i) parasitic resistance reduction and (ii) novel integration schemes.All layers were grown in a 300 mm ASM reduced pressure chemical vapor deposition reactor on Si(001) substrates and patterned substrates.Firstly, we will discuss the benefits of SiP growth at low temperature leading to high active doping concentrations (~1.1×1021 cm-3), as reported in our previous work [3]. Figure 1 shows the omega-2theta scans around the symmetric (004) reflections of the Si:P/Si stacks. As expected, reducing the Si precursor flow leads to a higher substitutional P (~7.5%) incorporation in the layer. The good crystallinity of the SiP layer is attested by the well-defined thickness fringes. Figure 2a represents the XRR scans of non-selective SiP process and selective SiP process compared to 100 nm bare SiO2 on Si substrate. The presence of fringes (red curve) indicates that a 2D amorphous SiP layer is deposited on SiO2. To confirm the full selectivity of the process and the absence of nuclei on the SiO2 surface, top view SEM was performed (cf. Figure 2b).Afterwards, we will focus on the SiGe:B epitaxy at low temperature. Figure 3a shows omega-2theta scans around the symmetric (004) reflections of the SiGe:B/Si stacks for various B flows. The apparent Ge content drops from 52.1% to around 41.3% when B flow was multiplied by 16. The inset represents the reciprocal space map (RSM) around the asymmetric (224) peak of SiGe:B layers grown on Si(001) substrates with the highest B flow. The RSM clearly indicates high quality and fully strained SiGe:B layer. Figure 3b depicts the apparent Ge drop vs B flow. This reduction in Ge content is attributed to B strain compensation effect leading to artificially lower Ge content [4]. Figure 3c represents SiGe:B layer resistivity vs B flow. Resistivity drops until a critical B flow and then increases with increasing B flow. Figure 4 shows active doping concentration and Hall mobility as function of the B flow. The Hall measurements were performed on a cleaved wafer edge and assume a Hall scattering factor of 1. Active carrier concertation increases with increased B flow. As a side effect of the higher activation, the Hall mobility is lowered likely due to an increase in ionized impurity scattering which is the reason why the resistivity does not decrease substantially below a certain value for higher B flows at current growth conditions. Layers with similar physical properties have resulted in S/D metal contact resistivity of ~5×10-10 Ohm.cm2 [5]. Figure 5 depicts the selective process on advanced patterned nanosheet test structures. Figure 5a illustrates the selectivity towards several nanosheet structures, Figure 5b shows a zoomed in image indicating selective process towards inner SiN spacers and SiO2. Figure 5c is a FFT of the SiGe:B area indicated by red square and Figure 5d is an EDS map of the key elements (Si, Ge, O, C, Cl, F, N). Figure 6a and 6b show the selective process stability over 20 runs. The HR-XRD measurements at wafer center are represented in Figure 6a. Figure 6b represents the resistivity at the wafer center. Thickness uniformity across one of the wafer is illustrated in Figure 6c. The results indicate excellent wafer to wafer and within wafer uniformities despite low temperature processing.LT epitaxy offers several advantages to reach high active doping concentrations and enable novel integration schemes. Despite challenges associated to LT epitaxy, in this work we showed the possibility to grow selective layers while maintaining the excellent physical layer properties, within wafer uniformity and wafer to wafer reproducibility.[1] H. Wu et al. EEE International Electron Devices Meeting (IEDM), (2018), pp. 35.4.1.[2] A. Vandooren et al. IEEE Symposium on VLSI Technology, (2018), pp. 69-70.[3] R. Khazaka et al. ECS Meeting s, MA2020-02(24), (2020) 1734-1734.[4] J.M. Hartmann et al. ECS JSST, 3(11) (2014) 382.[5] H. Xu et al. IEEE Symposium on VLSI Technology, (2022), (to be published). Figure 1