Investigation of ESD Protection in SiC BCD Process

Abstract

In order to develop electrostatic discharge (ESD) protection structures in Silicon Carbide (SiC) process, the ESD properties of SiC silicon-controlled rectifier (SCR), lateral-diffused MOS (LDMOS) and NMOS devices are reported in this paper. All devices were fabricated using Fraunhofer 4H-SiC Bipolar-CMOS-DMOS (BCD) process and characterized by transmission line pulse (TLP) system. The scalability of the failure current (I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t2</sub> ) of NMOS with multiple fingers is reported. The critical parameters (i.e. gate length and drift region) of LDMOS are varied to understand the effects on the triggering voltage and other ESD characteristics of the devices. The comparison of the I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t2</sub> between high voltage SCR (HV-SCR) and LDMOS has been investigated. TLP results show that HV-SCR structures have much higher I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t2</sub> than LDMOS structures. Cost-effective ESD protection structures can be designed by these HV-SCR devices. Furthermore, ESD characteristics of SiC HV-SCR and NMOS structures are simulated using Silvaco technology computer-aided design (TCAD) software.