Investigation of charge loss mechanisms in planar and raised STI charge trapping flash memories

Abstract

A comprehensive simulation to investigate the charge loss mechanisms in planar and raised STI NAND-type charge trapping flash (CTF) memories with careful calibrations is present. The tunneling and silicon nitride trap transport with Poole-Frenkel (PF) effect are solved self-consistently and validated based on the experimental data including gate stacks leakage, program speed, and high temperature retention. Based on the programmed state, the high temperature retention is simulated and compared with the measurement data. In planar CTF, the vertical charge loss through tunneling layers and blocking layers are analyzed. The results show that the former is the dominant one. Finally, the charge loss in raised STI CTF is compared with that in planar CTF. The results show that the enhanced charge loss in raised STI CTF is induced by the lateral spreading and the non-uniform charge storage nearby the STI edge, especially in the narrow width (100nm) raised STI CTF.