Investigation of Adiabatic Logic in Nano-meter Technology

Abstract

ABSTRACT With the increase in transistor integration in Very Large Scale Integration (VLSI) design, energy efficiency plays a major role as a design parameter. One of the key ideas used in reducing power consumption is by reducing the transistor switching. One of the effective solutions for achieving low power is by using an adiabatic logic style. As the technology grows, along with the device scaling, designers have to spend more time in debugging errors, which causes an increase in overall design and verification time. Since synchronisation of the power-clock phases is complex, the functional verification of four-phase adiabatic logic is time taking. A new adiabatic logic (MPFAL) based on positive feedback adiabatic logic (PFAL) circuit is proposed, which resolves the above problems. To show the feasibility of the proposed circuit, some available circuit styles like 2N2P, 2N-2N2P, differential cascode and pre-resolved adiabatic logic and PFAL are selected, and their power delay product at various frequencies (10–500 MHz) is compared with the proposed circuit. Monte Carlo simulation results show that the proposed circuit has better performance as compared to the existing adiabatic circuits.