A novel low power high speed positive feedback adiabatic logic

Abstract

Now a days, in the field of Very Large Scale Integration (VLSI), Power and Speed became more constrained parameters. In order to achieve better performance, one has to prefers low power and high speed designs only. This paper presents a novel design of Positive Feedback Adiabatic Logic (PFAL), which is extracted from previous adiabatic logic circuits such as PFAL and Modified PFAL. The proposed design exhibits less power and high speed over existing designs. A lot of research has been done on the adiabatic logic based designs and our design leads better results. This design can be used as the alternate circuit of PFAL in which this design plays a major role in present VLSI Technology based designs. The designs are simulated in 180nm CMOS Technology using Mentor Graphics EDA tools in ELDO and Schematic/Layout designed using Pyxis tool which is one of the tools.