Abstract
In this paper, we elaborated a relationship between the refresh time and the implantation overlap in capacitor region of planar P-MOS DRAM cell based on the retention time and the localized maximum electrical field. Several samples with different overlap distance from the implanted region in capacitor area and the edge of capacitor were prepared. It appeared that retention time enhanced about two times when the distance decreased from 0.13 to 0.05 μm due to reduced leakage current on the capacitor region. Raphael simulation revealed that the lowed local electric field resulted in reduction of leakage current.
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