Investigation Into How the Floor Plan Layout of a Manufactured PCB Influences Flip-Chip Susceptibility to Vibration

Kangkana Baishya,Guangming Zhang,Derek Richard Braden,David Mark Harvey

doi:10.1109/tcpmt.2020.2987334

Kangkana Baishya, Guangming Zhang + Show 2 more

Open Access

https://doi.org/10.1109/tcpmt.2020.2987334

Copy DOI

Abstract

This article investigates how floor plan layout of a printed circuit board (PCB) influences the reliability of the component's solder joint connections when operated in a vibrating environment. A random vibration profile as seen in an automotive environment was used in full lifetime tests. An industry-standard FR4 PCB with electroless nickel immersion gold (ENIG) surface finish was manufactured with double-sided component placement including 14 flip chips, eight on the top side and six on the bottom side. Ultrasound scans were used as a nondestructive test to assess the integrity of solder joints from manufacture to failure. This enabled monitoring of the important interface between solder joints and flip chip where failure mostly occurs. The initial failure pattern was found by experiment where 86 cycles of random vibration caused all flip chips to mechanically fail. Failure followed a Weibull probability with a value of β = 1.297, indicating that failure rates increase with time. The results show that the reliability of a flip chip varies with its position on a PCB with some marked differences to component lifetimes. The results also show that for two-sided flip-chip placements on a PCB, back-to-back, overlapped, and single-sided orientations have subtle effects on flip-chip lifetimes. Similarly, reliability varied with solder joint positions since joints on the sides of a flip chip nearest the PCB edges were less reliable than those on sides on a flip chip furthest away. Finally, design guidelines are offered to effect the most reliable flip-chip placement on a two-sided PCB when operated in a vibrating environment.

Highlights

S OLDER joint fatigue failure under vibration loading has always been a great concern in the microelectronics industry
It can be safely concluded that in a printed circuit board (PCB), flip chips with backto-back connections with no offset are the most reliable, while standalone flip chips with no back-to-back connections, especially the ones placed near the center of the PCB, are the least reliable when considering their susceptibility to vibration cycling
The effects of vibration cycling on the reliability of flip chips of different positions and relative orientations in an industry-grade PCB were evaluated

Summary

INTRODUCTION

S OLDER joint fatigue failure under vibration loading has always been a great concern in the microelectronics industry. Wong [9] presented a methodology to characterize and predict fatigue failure of BGA package solder joints under vibration loading based on board strain versus number-of-cycles-to-failure (or S–N) curve. Che and Pang [10] carried out some sinusoidal vibration reliability tests for flip-chip solder joints and applied a linear cumulative damage analysis method (Miner’s rule) to predict the life of solder joints. None of these studies attempted to conduct real-time vibration tests or were able to monitor the exact dynamics of manufactured solder joint reliability. PCB floor plan design guidelines for the most secure flip-chip placement for systems working in a vibration environment are proposed, which will ensure better reliability and improved lifetimes of PCBs in a vibration environment

EXPERIMENTAL DESIGN

Weibull Analysis

Reliability Analysis Based on Flip-Chip Position

Design Guidelines for Floor Plan Layout in a PCB

CONCLUSION