Investigating the performance of SiGe embedded dual source p-FinFET architecture

Abstract

In this work, a modified Fin shaped Field Effect Transistor (FinFET) structure has been proposed with dual SiGe embedded extended source regions. Comparative simulation studies with SiGe embedded source/drain conventional single Fin channel and dual Fin channel FinFET structure having similar device footprint area shows almost 3× and 1.5× improvement of drive current respectively and lower threshold voltage in the proposed architecture. The dual extended SiGe source regions and presence of Si drain in the vertical direction of the channel generate bi-axial channel stress which improves the channel charge density, which results in improvement in drive current significantly. Also it has been observed from various simulation studies that the separated gate regions increase the inversion current density in the channel which also leads to improvement of the device performance.