Investigating the performance of CNFET using 10T SET D-Flip flop

E Raguvaran,K S Nithyananda Vishnu,S Hema Chitra

doi:10.1109/iccci.2012.6158882

Investigating the performance of CNFET using 10T SET D-Flip flop

E Raguvaran, K S Nithyananda Vishnu + Show 1 more

https://doi.org/10.1109/iccci.2012.6158882

Copy DOI

Publication Date: Jan 1, 2012

#Carbon Nanotube Field Effect Transistors #Carbon Nanotube Field Effect Transistors Model + Show 8 more

Abstract
Full-Text PDF
Similar Papers

Abstract

This paper investigates the performance of Single Edge Triggered D-Flip flop (SET D-FF) using Carbon Nanotube Field Effect Transistors (CNFETs). The circuit performance of CNFET model has been compared with that of silicon based MOSFET model. CNFET circuit models are tested for various substrate bias voltages in sub threshold region. A 10 Transistor version of SET D-FF is implemented using PTM 32nm CMOS model and Stanford single-walled CNFET model and simulated using HSPICE. The performance parameter under investigation is Power Delay Product (PDP). The comparative simulation result at various frequencies show that CNFET SET DFFs have superior Power Delay Product over MOSFET SET DFFs.

Full Text