Abstract
With the development of Non-Volatile Memory (NVM) technologies in recent years, several studies suggest using them as an alternative for SRAMs in on-chip caches. One of the main challenges in replacing SRAMs with NVMs is limited endurance of NVMs (i.e. the maximum allowed number of write operations in an NVM cell). The endurance of NVM caches is directly affected not only by workload behaviors, but also by process variations (PVs). Several studies characterized the endurance of NVM caches but they do not consider the simultaneous effects of the PVs and the workloads. In this paper, we propose a high-level framework to investigate the endurance of NVM caches affected by the per-cell endurance as well as the workloads behaviors and PVs. This framework is an augmentation of gem5 simulator. The investigations reveal that compared with ideal NVM cache, 20% PVs in manufacturing the NVM cache can decrease the endurance by 250x, on average. Meanwhile, the endurance of the cache varies for different workloads by several orders of magnitude.
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