Investigating the behavior of physical defects in pn-junction based reconfigurable graphene devices

Abstract

Graphene, one of the viable candidates to replace Silicon in the next generation electronic devices, is pushing the research community to find new technological solutions that can exploit its special characteristics. Among the proposed approaches, the electrostatic doping represents a key option. It allows the implementation of equivalent pn-junctions through which is possible to build a new class of reconfigurable logic gates, the devices analyzed in this work. Recent works presented a quantitative analysis of such gates in terms of area, delay and power consumptions, confirming their superiority w.r.t. CMOS technologies below the 22nm. This work explores another dimension, that is testability, and proposes a study of possible physical defects that might alter the functionality of the graphene logic gates. The electrical behavior of faulty devices, obtained through the emulation of physical failures at the SPICE-level, has been analyzed and mapped at a higher level of abstraction using proper fault models. Most of such models belong to the CMOS domain, but for some specific class of defects, new fault definitions are needed.