Investigating simulation of hardware at various levels of abstraction and timing back-annotation of dataflow descriptions

Abstract

Digital hardware can be described at various levels of abstraction. Functional descriptions merely capture the behavior of the circuit without revealing the details of the architec ture. On the other hand, the gate or switch level models are more robust and include great amounts of detail about the circuit (timing and architecture). Functional models are attractive because they simulate faster than low level models. However, the tradeoff is that the simulation results are not as accurate (primarily from the timing standpoint) as those obtained from low level models. Clearly, having a model that simulates as fast as the functional model and produces accuracies comparable to those of gate level models is desirable. This paper is an investigation of achieving such models. Two levels of abstractions, dataflow and gate level, are considered and the VHDL language (an industry standard) is used for describing Finite State Machine circuits at both levels. Feasibility of timing back-annotation of dataflow models with the information obtained from gate level is analyzed.