Abstract
A new design of CMOS current comparator with emphasis on low input offset current and low power consumption is described. Its unique approach is the use of identical inverting amplifiers to operate as transimpedance amplifier and voltage comparator that guarantees zero input offset current independent of how the inverting amplifier is implemented. This allows the amplifier to be just a simple NMOS driving PMOS current load enable a power delay trade off by adjusting the load current. This amplifier topology can also operate at DC power supply as low as 0.75V and in subthreshold region to achieve highest gain. Simulation using 0.18μm process, 1V DC supply, and 25nA load shows that it can outperform other existed works with an input offset current of less than 1pA under all standard PVT variations.
Published Version
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