A Low Voltage CMOS Current Comparator with Offset Compensation

Abstract

Analysis and design of an inverter-based current comparator consisting of 3 cascaded inverters is presented. Ideally, the comparator has almost zero input offset current when all inverters are assumed to be identical. In practice, small amount of threshold voltage or current mismatches may cause the offset current to increase dramatically. A switched-capacitor inverter is added to the comparator circuit in order to mitigate such effect. During compensation phase, the switched inverter forms a feedback loop to generate a current that will compensate the input offset current. During comparison phase, the generated charge hold in the capacitor decreases the offset current significantly. To keep the loop stable, an R-C Miller's frequency compensator is also added. A prototype of the whole circuit using 0.18µm process is designed and analyzed to prove this concept. It operates at 1V DC supply with 870nA consumption, 1nA resolution and 50ns delay for ±100nA step input. Its input offset current is 13pA when there is no mismatch. When the mismatch is accounted, it increases to 164nA. After installation of the compensation circuit, the offset current is cut down to 19pA.