Inverse modeling of two-dimensional MOSFET dopant profile via capacitance of the source/drain gated diode

Abstract

This paper proposes and demonstrates a new approach to two-dimensional (2-D) dopant profile extraction for MOSFETs by treating the source/drain-to-substrate junction as a gated diode. The small-signal capacitance of the diode measured as a function of gate and source/drain bias is used as the target to be matched in an inverse modeling process. It is shown that this capacitance allows both the substrate dopant profile in the channel region and the source/drain-to-substrate profile parallel to the surface to be evaluated with a single set of measurement data. Experimental results for n-MOSFET's with drawn channel length =1 /spl mu/m and 0.265 /spl mu/m are presented. Comparison of other electrical measurement with simulation data based on the extracted profile is also given.