Inverse Integer Transform in H.264/AVC Intra-frame Encoder

Abstract

Real-time video compression applications such as Digital Video Camera (DVC), Television Studio Broadcast, and Surveillance video utilize the H.264/AVC video encoder in intra-only encoding mode. The H.264/AVC standard supports multiple intra-prediction modes to reduce spatial redundancy in the video frame. The intra-prediction process for a current pixels block requires the reconstructed pixels from the previously encoded blocks within the same video frame. Therefore, processing units with low latency and high-throughput are required in the processing chain of the intra-frame encoder to meet the real-time performance constraint. The inverse integer transform is on the critical path of the intra-frame encoder and is one of the compute-intensive processing unit in the intra-frame encoding loop. In this paper, for real-time video compression applications, we propose a low-latency, area-efficient and high-throughput inverse integer transform hardware architecture. The proposed design significantly reduces the latency penalty (2:67ns) of the inverse integer transform in the intra-frame processing chain. While working at clock frequency of 375 MHz, synthesized under 0:18um CMOS standard cell technology, it can easily meet the throughput requirement of real-time processing of HDTV resolutions and consumes only 7512 gates.