An efficient realization of forward integer transform in H.264/AVC intra-frame encoder

Abstract

The H.264/AVC intra-only frame encoder, for its excellent encoding performance, is well-suited for image/video compression applications such as Digital Still Camera (DSC), Digital Video Camera (DVC), Television Studio Broadcast and Surveillance video. The forward integer transform is an integral part of the H.264/AVC video encoder. In this paper, for image compression applications running on battery-powered electronic devices (such as DSC), we propose a low-power, area-efficient realization of the forward integer transform. The proposed solution reduces the number of operations by more than 50% (30 vs. 64) and consumes significantly less dynamic power when compared with existing state-of-the-art designs for the forward integer transform. For video compression applications such as Television Studio Broadcast or Surveillance Videos, where throughput is more important, we propose a low-latency, area-efficient realization of the forward integer transform unit in the intra frame processing chain. With the proposed solution, the effective latency for forward integer transform is drastically reduced, as the processing unit is no longer on the critical path of the intra-frame processing chain. Moreover, the proposed solution requires half the numbers of operations for its hardware implementation, when compared with existing state-of-the-art designs for forward integer transform.