Introduction to Quantum Transport

Abstract

Since the introduction of integrated circuits, the number of individual transistors on a single chip has doubled approximately every three years. Today, we are talking about multimegabit DRAM memories (the 16 Mb is on the market, the 64 Mb is in pre-production, and research versions of the 256 Mb have been demonstrated) and dense signal-processing chips with comparable component density. At the rate of progress of dynamic memory (DRAM), we can expect to reach chip densities of 109 devices by 2001. By 2020, we may well need to have memory chips with 1 Tb. In general, progress in the integrated circuit field has followed a complicated scaling relationship. The reduction of design rule (or effective gate length) proceeds approximately by a factor of 1.4 each generation (which produces only an increase of 2x in density, the remainder coming from circuit enhancements and larger chip size). This means we will be using 0.1–0.15 urn rules for the 4 Gb chips (the 256 Mb chip will use 0.25 urn design rules). If we continue this extrapolation, current technology will require 30 nm design rules, and a cell size < 103 nm2, for a 1 Tb memory chip.KeywordsDensity MatrixMonte CarloWigner FunctionGate LengthQuantum TransportThese keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.