Abstract
The requirements of high speed and performance and cost effectiveness demand of VLSI chips a continuing push in miniaturization. As a consequence, the design rule (or the effective gate length) has been reduced from several microns down to < 0.1 μm envisioned within a few years. While the expected 256 Mb chip requires the use of quarter micron design rules, it is expected that we will need 0.1–0.15 μm rules for gigabit chips, and the extrapolation of the down scaling trends will extend the design rules to sub-0.1 μm for a terabit memory chip in the near future. With this scenario for VLSI technology development, the deep understanding of the device physics governing device operation is the key to successful device design, as different physical mechanism impose different level of effects on different device scales.
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