Introducing 65 nm CMOS technology in low-noise read-out of semiconductor detectors

Abstract

The large scale of integration provided by CMOS processes with minimum feature size in the 100 nm range, makes them very attractive in the design of front-end electronics for highly pixelated detectors, where several functions need to be packed inside a relatively small silicon area. Nowadays, processes with 130 nm minimum channel length are widely available for Application Specific Integrated Circuits (ASICs) design, nonetheless designers are considering more scaled technologies following the trend of commercial silicon foundries. This work provides an extensive analysis of the noise performance which can be attained by detector front-end circuits in a 65 nm CMOS process. The behavior of the 1/ f and white noise terms in this technology node is studied as a function of the device polarity, of the gate length and width and of the bias conditions. A comparison with data from previous CMOS generations is also carried out to evaluate the impact of scaling down to the 65 nm node.