Intrinsic noise in aggressively scaled field-effect transistors

Abstract

According to roadmap projections, nanoscale field-effect transistors (FETs) with channellengths below 30 nm and several gates (for improving their gate control over thesource–drain conductance) will come to the market in the next few years. However, fewstudies deal with the noise performance of these aggressively scaled FETs. In this work, astudy of the effect of the intrinsic (thermal and shot) noise of such FETs on theperformance of an analog amplifier and a digital inverter is carried out by means ofnumerical simulations with a powerful Monte Carlo (quantum) simulator. The numericaldata indicate important drawbacks in the noise performance of aggressively scaledFETs that could invalidate roadmap projections as regards analog and digitalapplications.