Intrinsic ESD robustness on new high voltage N/PMOS devices in 28 nm FDSOI UTBB CMOS technology through TLP/VFTLP characterizations

Abstract

The robustness of intrinsic electrostatic discharge (ESD) is a major topic for the fabrication of advanced CMOS technology and in particular for high voltage (HV) N/PMOS transistors. In this study, it is reported the way to fabricate a HV MOS in standard 28 nm fully depleted (FD) silicon on insulator (SOI) with ultra-thin body and BOX (UTBB). This new device is without extra technology steps and without extra cost. This solution is based on layout design approaches with different flavours of back gate. Afterwards, DC characterizations on booth N & P MOS transistors are presented and discussed. The next step is to investigate the intrinsic ESD robustness on these devices through transmission line pulse (TLP) characterization at room temperature. It appears an interesting intrinsic robustness for this kind of devices. These preliminary results will be useful to use these devices in HV applications with a dedicated ESD protection and this solution lead to be more competitive on FDSOI technology nodes.