Intra- and Inter-Chip Transmission of Millimeter-Wave Interconnects in NoC-Based Multi-Chip Systems

Rounak Singh Narde,Jayanti Venkataraman,Amlan Ganguly,Ivan Puchades

doi:10.1109/access.2019.2931658

Rounak Singh Narde, Jayanti Venkataraman + Show 2 more

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https://doi.org/10.1109/access.2019.2931658

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Journal: IEEE Access	Publication Date: Jan 1, 2019
Citations: 56	License type: CC BY 4.0

Affiliation: Rochester Institute of Technology

Abstract

The primary objective of this paper is to investigate the communication capabilities of short-range millimeter-wave (mmWave) communication among network-on-chip (NoC)-based multi-core processors integrated on a substrate board. This paper presents the characterization of transmission between on-chip antennas for both intra- and inter-chip communication in multi-chip computing systems, such as server blades or embedded systems. Through simulation at 30 GHz, we have characterized the inter-chip transmission and studied the electric field distribution to explain the transmission characteristics. It is shown that the antenna radiation efficiency reduces with a decrease in the resistivity of silicon. The simulation results have been validated with fabricated antennas in different orientations on silicon dies that can communicate with inter-chip transmission coefficients ranging from −45 to −60 dB while sustaining bandwidths up to 7 GHz. Using measurements, a large-scale log-normal channel model is derived, which can be used for system-level architecture design. Using the same simulation environment, we perform design and analysis at 60 GHz to provide another non-interfering frequency channel for inter-chip communication in order to increase the physical bandwidth of the interconnection architecture. Furthermore, densely packed multilayer copper wires in NoCs have been modeled in this paper to study their impact on the wireless transmission for both intra- and inter-chip links. The dense orthogonal multilayer wires are shown to be equivalent to copper sheets. In addition, we have shown that the antenna radiation efficiency reduces in the presence of these densely packed wires placed in the close proximity of the antenna elements. Using this model, the reduction of inter-chip transmission is quantified to be about 20 dB compared with a system with no wires. Furthermore, the transmission characteristics of the antennas resonating at 60 GHz in a flip-chip packaging environment are also presented.

Highlights

Various kinds of computing platforms such as server blades or embedded systems are essentially platform-based multichip systems that integrate many multicore processor chips, memory banks and other functional units
The computing community has recognized the need for non-traditional solutions to the interconnect problem, most system-level work relies only on simulation of the antenna propagation characteristics in simplified environments [12], [13]. This motivates our work in this paper, where we investigate the capabilities of mmWave communication for short-range links among chips integrated on a typical substrate, especially in the presence of realistic structures like wired interconnects and ground plane
We do not adopt beam-forming antenna arrays, which are the common focus for mmWave systems in other application areas such as 5G communications [36]. Such mmWave antennas, which are fabricated using top layer metals of CMOS processes, are suitable for near-term solutions to the wired interconnect problem compared to other alternatives like Graphene or Carbon Nanotube (CNT) based antennas, they might operate at higher frequencies [37]

Summary

Introduction

Various kinds of computing platforms such as server blades or embedded systems are essentially platform-based multichip systems that integrate many multicore processor chips, memory banks and other functional units. With the increase in the computational and functional complexity of these plat-. Forms, the number of individual System-on-Chips (SoCs) or multicore processing chips in such systems increase manifold. This makes the interconnection in these systems grow in both size and complexity. While intra-chip communication infrastructure is seeing a paradigm shift from busbased systems to Network- on-Chip (NoC) architectures [1], inter-chip communication needs to evolve at a rapid pace to cater to increasing bandwidth demands within the strict power and thermal envelopes.

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