Interposer design optimization for high frequency signal transmission in passive and active interposer using through silicon via (TSV)

Abstract

New concept of interposer in FPGA system will be introduced. The interposer includes a lot of TSVs for the high speed signals. Technology requirements and manufacturing process to support multi-gigabit or tens-of-gigabit per second SerDes application will be presented. The interposer needs to be accurately modeled over the high frequency by considering all those requirements before design optimization. An interposer test vehicle was fabricated for measurement and verification. The measurement technique using vector network analyzer including de-embedding process will be introduced. At the same time, TSV high frequency modeling methodology will be disclosed. Both broadband s-parameter model and RLC lumped model based on physical structures were generated. The interposer could be a passive component or an active component with circuit. The passive interposer has an advantage in a certain area and the active interposer also has its own. The depletion area in silicon substrate will be considered as well to increase the level of accuracy. The routing metal loss in under bump metallurgy (UBM) layer should be analyzed also. Finally, full channel analysis has been done. It includes optimized interposer model on top of package substrate and printed circuit board. Each proposed interposer structure enables high performance signaling and great visibility in both passive and active interposer.