Abstract
Nowadays, designs become more and more complex and are often developed by several teams that may use different Hardware Description Languages. Mixed Verilog/VHDL designs are proliferating because teams choose different languages or because they are importing intellectual property libraries of VHDL or Verilog cells. The authors of paper [1] which compares Verilog and VHDL semantics conclude that there is enough overlap between the two languages for tools vendors to consider building bilingual tools such as compilers, simulators etc... In this paper we analyze the requirements for a mixed language GUI and explain how the compatibility and interoperability of the standard Verilog and VHDL language procedural interfaces was key to build SimVision, Cadence NCSimulator graphical debugging and verification environment. The principles highlighted in this paper can also be applied to other kinds of applications such as Verilog/VHDL cosimulation, testbench generation etc... In the following, we will focus on the problems inherent to a Verilog/VHDL GUI development. In a mixed language design, the language boundaries are very clearly defined and language construct mixing exist only at the instance level. VHDL can be instantiated from within a Verilog module and Verilog modules can appear as sub-instances of a VHDL instance. Usually, models are integrated by the generation of a shell or by direct instantiation. The shell methodology seems to be the preferred way for importing foreign models. A shell is the interface to the model and is written in the HDL language of the instantiating parent scope. A shell does not add an extra level of design hierarchy; it simply places the behavior of the imported model in the design. The shell bridges the differences in the language syntax and creates correspondence between the language constructs. All communication issues between the languages are localized in the shell. In the case where a shell interfaces a VHDL description to a Verilog environment, the shell is a Verilog compliant module definition equivalent to the VHDL entity description. The shell only specifies the interface (ports, parameters) while the behavior is left expressed in VHDL. This constitutes a typical mixed language use model. In this model, the challenges for a debug and verification environment are: 1) to have the capability to refer to, select any object, whether it belongs to a Verilog or VHDL instance, 2) to be able to navigate through the hierarchy and follow net connections in either language domains, 3) to be able to set, get the value of any object in the design, 4) to have a language sensitive graphical debug context (menus, messages) which adapts to the user actions.
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Published Version
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