Interfacial capacitance in lithium disilicate glass: Experimental factors and charge carrier density

Abstract

AbstractThe formation of an electric double‐layer (EDL) is an important phenomenon for many research areas, including energy storage technology. Although EDL is well‐known in electrochemistry, most of the studies involve the characterization of liquid electrolyte/electrode interfaces, and only a limited number of studies in solid‐solid contacts, such as solid electrolyte/electrode interface are available. This paper employed electrochemical impedance spectroscopy (EIS) to systematically investigate the influence of experimental factors in the interfacial capacitance arising from the electrode polarization in a lithium disilicate glass/gold electrode interface. It analyzed the influence of a.c. input voltage amplitude, samples' roughness (mechanical and chemomechanical polishing) and thickness, range of applied frequency and temperature, and the number of impedance cycles. In short, it was found that an input voltage range of 15–60 mV is indicated to minimize potential electrochemical processes during electrode polarization, where the data is reproducible from the second measurement cycle onward. Smoother surfaces closely approximated ideal electrode spike behavior, with surface treatment exhibiting influence on interfacial capacitance values. Moreover, as expected, we observed an increase in relative permittivity values with increasing thickness, accompanied by decreased capacitance values. Finally, by employing optimal experimental conditions and analyzing the inflection frequency () of the versus log() curve, we determined that the ratio between effective charge carriers () and the total number of charge carriers () falls within the range of 5–12% between 130°C and 280°C.