Interface properties of Si3N4Si/n-GaAs metal-msulator-semiconductor structure using a Si interlayer

Abstract

Abstract We report the effects of Si interlayer on the capacitance-voltage (C─V) characteristics of Si3N4/Si/n-GaAs metal-insulator-semiconductor (MIS) capacitor as a function of interfacial Si thickness, Si growth temperature and post-growth annealing. The thickness of interfacial Si was found to be the most pivotal parameter for the best interface properties as determined by the comprehensive C─V and conductance measurements. The minimum interface trap density D it of 5×1010eV−1cm−2 near midgap is realized with a Si interlayer of 10 A. The hysteresis and frequency dispersion of the GaAs MIS capacitor were lower than 50 mV, and some of them as low as 30 mV under a field swing of about ±l·3MVcm−1. Ex-situ solid-phase annealing (SPA) at 550°C in N2 using rapid thermal annealing was sufficient to recrystallize the as-deposited Si interlayer at a low temperature (less than 400°C). The minimum D it thus obtained using ex-situ SPA was less than 1·5 × 1011 eV−1 cm−2 regardless of Si deposition temperature. 1 MH...